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Wednesday, February 27, 2013

The Stanford 256x256 CMOS Image Sensor with ΔΣ-Based Single-Shot Compressed Sensing

Like everybody else. I love a good PR when I see one. It first showed up on my radar screen with Vladimir's blog then on my Google alert. IEEE Spectrum is featuring a blurb on Camera Chip Makes Already-Compressed Images, I had mentioned before and found the conference paper.Here it is A 256x256 CMOS Image Sensor with ΔΣ-Based Single-Shot Compressed Sensing by Y. Oike and A. El Gamal, the abstract reads:

A CMOS image sensor architecture with built-in single-shot compressed sensing is described. The image sensor employs a conventional 4-T pixel and per-column ΣΔ ADCs. The compressed sensing measurements are obtained via a column multiplexer that sequentially applies randomly selected pixel values to the input of each ΣΔ modulator. At the end of readout, each ADC outputs a quantized value of the average of the pixel values applied to its input. The image is recovered from the random linear measurements off-chip using numerical optimization algorithms. To demonstrate this architecture, a 256x256 pixel CMOS image sensor is fabricated in 0.15 μm CIS process. The sensor can operate in compressed sensing mode with compression ratio 1/4, 1/8, or 1/16 at 480, 960, or 1920 fps, respectively, or in normal capture mode with no compressed sensing at a maximum frame rate of 120 fps. Measurement results demonstrate capture in compressed sensing mode at roughly the same readout noise of 351 μVrms and power consumption of 96.2 mW of normal capture at 120 fps. This performance is achieved with only 1.8% die area overhead. Image reconstruction shows modest quality loss relative to normal capture and significantly higher image quality than downsampling.

Since I hadn't read the actual paper, I wondered how this architecture was different from either the EPFL CMOS architecture or simply the Georgia Tech Transform Imager, an anonymous commenter responded with:

From the paper:
"In [18], [19] (the EPFL implementation), CS is implemented by shifting a random digital pattern representing a measurement matrix via a shift register distributed over the pixel array (see Fig. 1(d)). The currents from the pixels with the pattern in the same column are summed over one line while the currents from the pixels with the pattern are summed over a second column line. The total weighted sum is then performed again in analog at the chip level. This implementation requires multiple shot image capture, is not scalable due to the large pixel size, and suffers from low SNR due to pixel design and analog summation."

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